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zilog worldwide headquarters ? 532 race street ? san jose, ca 95126-3432 telephone: 408.558.8500 ? fax: 408.558.8300 ? www.zilog.com preliminary product specification ps008808-1203 z86l825/826/827 20-pin low-voltage ir microcontrollers
p r e l i m i n a r y ps008808-1203 this publication is subject to replacement by a la ter edition. to determine whether a later edition exists, or to request copies of publications, contact: zilog worldwide headquarters 532 race street san jose, ca 95126-3432 telephone: 408.558.8500 fax: 408.558.8300 www.zilog.com zilog is a registered trademark of zilog inc. in the unit ed states and in other countri es. all other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. document disclaimer ?2003 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible us es and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not a ssume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. devi ces sold by zilog, inc. are covered by warranty and limitation of liability provisions a ppearing in the zilog, inc. terms and conditions of sale. zilog, inc. makes no warranty of merchantability or fitness for any purpose. e xcept with the express writt en approval of zilog, use of information, devices, or technology as critical components of life support syst ems is not authorized. no licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y iii table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 xtal1 crystal 1 (time-based input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 xtal2 crystal 2 (time-based output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 port 0 (p00,01,07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 port 2 (p27?p20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 port 3 (p36?p31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 comparator inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 expanded register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 counter/timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 counter/timer functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 port configuration register (pcon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 stop-mode recovery register (smr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 stop-mode recovery register 2 (smr2) . . . . . . . . . . . . . . . . . . . . . . . . . . 63 watch-dog timer mode register (wdtmr) . . . . . . . . . . . . . . . . . . . . . . . . 64 mask selectable options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 brown-out voltage/standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y iv ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 z86l825/826/827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 precharacterization product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 customer feedback form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 z86l825/826/827 20-pin low-voltage ir microcontrollers . . . . . . . . . . . . . 72 customer information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 product information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 return information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 problem description or suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y v list of figures figure 1. counter/timers diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. 20-pin dip/soic/ssop pi n assignment . . . . . . . . . . . . . . . . . . . . . 5 figure 4. test load diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. port 0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. port 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. port 3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. port 3 counter/timer output configuration . . . . . . . . . . . . . . . . . . . 18 figure 10. program memory map (32k rom) . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. expanded register file architecture . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. register pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13. tc8 control register?(0d) oh: read/write except where noted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14. t8 and t16 common control functions?(0d) 1h: read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 15. t16 control register?(0d) 2h: read/write except where noted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 16. stop-mode recovery register?(0f) 0bh: d6?d0 = write only, d7 = read only . . . . . . . . . . . . . . . . . . . . . . . 25 figure 17. stop-mode recovery register 2?(0f) 0dh: d2?d4, d6 write only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 18. watch-dog timer register?(0f) 0fh: write only . . . . . . . . . . . . . 26 figure 19. port configuration register (pcon)?(0f) 0h: write only . . . . . . . 27 figure 20. port 2 mode register?f6h: write only . . . . . . . . . . . . . . . . . . . . . 27 figure 21. port 3 mode register?f7h: write only . . . . . . . . . . . . . . . . . . . . . 27 figure 22. port 0 and 1 mode register (f8h: write only) . . . . . . . . . . . . . . . . 28 figure 23. interrupt priority register?f9h: write only . . . . . . . . . . . . . . . . . . 29 figure 24. interrupt request register?fah: read/write . . . . . . . . . . . . . . . . 29 figure 25. interrupt mask register?fbh: read/write . . . . . . . . . . . . . . . . . . . 30 figure 26. flag register?fch: read/write . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 27. register pointer?fdh: read/write . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 28. stack pointer high?feh: read/write . . . . . . . . . . . . . . . . . . . . . . 31 figure 29. stack pointer low?ffh: read/write . . . . . . . . . . . . . . . . . . . . . . . 31 figure 30. register pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y vi figure 31. glitch filter circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 32. 8-bit counter/timer circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 33. transmit mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 34. t8_out in single-pass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 35. t8_out in modulo-n mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 36. demodulation mode count capture flowchart . . . . . . . . . . . . . . . . 47 figure 37. demodulation mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 38. 16-bit counter/timer circ uits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 39. t16_out in single-pass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 40. t16_out in modulo-n mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 41. ping-pong mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 42. output circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 43. interrupt block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 44. oscillator confi guration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 45. port configuration register (pcon)?write only . . . . . . . . . . . . . . 58 figure 46. stop-mode recovery register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 47. sclk circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 48. stop-mode recovery source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 49. stop-mode recovery register 2?(0f) dh:d2?d4, d6 write only 63 figure 50. watch-dog timer mode register?write only . . . . . . . . . . . . . . . . 65 figure 51. resets and wdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 52. 20-pin soic package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 53. 20-pin dip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 54. 20-pin ssop package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 55. ordering codes example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y vii list of tables table 1. z86l825/826/827 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. power conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 3. 20-pin dip, soic, and ssop pin identification . . . . . . . . . . . . . . . . 5 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 5. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 6. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 7. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8. pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. expanded register group d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 10. hi8(d)0bh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 11. l08(d)0ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 12. hi16(d)09h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 13. l016(d)08h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14. tc16h(d)07h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 15. tc16l(d)06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 16. tc8h(d)05h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 17. tc8l(d)04h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 18. ctr0 (d)00 counter/timer8 control register . . . . . . . . . . . . . . . . 36 table 19. ctr1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 20. ctr2 (d)02h: counter/timer16 control register . . . . . . . . . . . . . . 41 table 21. interrupt types, sources, and vectors . . . . . . . . . . . . . . . . . . . . . . 54 table 22. irq register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 23. stop-mode recovery source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 24. smr2(f)0dh: stop-mode recovery register 2 . . . . . . . . . . . . . . . 64 table 25. wdt time select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 26. mask selectable options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 1 features table 1 shows some of the features of the z86l825/826/827 microcontrollers. ? low power consumption?60 mw (typical) ? three standby modes ? stop?2 a ? halt?0.8 ma ? low voltage ? special architecture to automate both generation and reception of complex pulses or signals: ? one programmable 8-bit counter/timer with two capture registers and two load registers ? one programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair ? programmable input glitch filter for pulse reception ? six priority interrupts ? three external ? two assigned to counter/timers ? one low battery voltage detection interrupt ? low battery voltage detection with flag ? programmable watch-dog/power-on reset circuits ? two independent comparators with programmable interrupt polarity table 1. z86l825/826/827 features device rom (kb) ram* (bytes) i/o lines voltage range z86l825 4 237 16 2.0 v to 3.6 v z86l826 8 237 16 2.0 v to 3.6 v z86l827 16 237 16 2.0 v to 3.6 v note: *general purpose
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 2 ? mask selectable 200 50% k ? transistor pull-ups on ports 2 and 3. port 0 always has pull-up selected. ? programmable mask options: ? oscillator selection: rc oscillator versus crystal or other clock source ? oscillator operational mode: norma l high-frequency operation enabled or 32-khz operation enabled ? port 2: 0?7 pull-ups ? port 3: pull-ups ? port 0: 0?3 mouse mode: normal mode(.5v dd input threshold) versus mouse mode (.4v dd input threshold) general description the z86l825/826/827 are rom-based members of the z8 mcu single-chip fam- ily of ir (infrared) with 237 bytes of general-purpose ram and 4 kb of rom. zilog?s cmos microcontrollers offer fast executing, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up transistors. the z86l825 architecture is based on zilog's 8-bit microcontroller core with an expanded register file to allow access to register mapped peripherals, i/o cir- cuits, and powerful counter/timer circuitry. the z8 offers a flexible i/o scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many consumer, au tomotive, computer peripheral, and battery operated hand-held applications. the register file consists of 256 bytes of ram. it includes three i/o port registers, 16 control and status registers and the rest are general purpose registers. regis- ter feh (sph) can be used as general purpose register. the expanded register file consists of two additional register groups (f and d). the z86l825 offers a new intelligent counter/timer architecture with 8-bit and 16- bit counter/timers (figure 1). also included are a large number of user-selectable modes, and two on-board comparators to pr ocess analog signals with separate reference voltages.
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 3 figure 1. counter/timers diagram all signals with an overline, ? ?, are active low. for example, b/w , in which word is active low), and b /w, in which byte is active low. power connections follow the conventions listed in table 2. figure 2 shows the functional block diagram. table 2. power conventions connection circuit device power v cc v dd ground gnd v ss hi 16 lo 16 8 8 16-bit t 16 16 timer 16 1248 sclk clock divider 8 8 tc16h tc16l and/or logic timer 8/16 input glitch filter edge detect circuit 8-bit t8 8 8 tc8h tc8l timer 8 8 8 hi8 lo8 note:
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 4 figure 2. functional block diagram p00 p01 p07 port 0 p20 p21 p22 p23 p24 p25 p26 p27 port 2 i/o bit programmable counter/timer 8 8-bit expanded register file rom 4/8/16k x 8 internal address bus register file 256 x 8-bit machine timing and instruction control counter/timer 16 16-bit p31 p32 p33 p34 p36 internal z8 core expanded register bus power xtal v dd v ss register bus port 3 data bus
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 5 pin description the pin assignment for the 20-pin dual in -line package (dip)/small outline inte- grated circuit (soic)/shrink small outline package (ssop) is shown in figure 3. the pins are identified in table 3. figure 3. 20-pin dip/so ic/ssop pin assignment table 3. 20-pin dip, soic, and ssop pin identification 20-pin dip/soic/ssop standard mode direction description 1 p25 input/output p20-27 are bit configurable as input or output. 2 p26 input/output p20-27 are bit configurable as input or output. 3 p27 input/output p20-27 are bit configurable as input or output. 4 p07 input/output port 07 is configurable as input or output 5v dd power supply 6 xtal2 output crystal, oscillator clock 7 xtal1 input crystal, oscillator clock 8 p31 input irq2/modulator input 9 p32 input irq0 10 p33 input irq1 11 p34 output t8 output 12 p36 output t8/t16 output 13 p00 input/output port 00,01 are configurable as input or output 14 p01 input/output port 00,01 are configurable as input or output 15 v ss ground 16 p20 input/output p20-27 are bit configurable as input or output. p24 p23 p22 p21 p20 v ss p01 p00/pref1 p36 p34 p25 p26 p27 p07 v dd xtal2 xtal1 p31 p32 p33 1 20 x86l825/826/827 dip/soic/ssop 10 11 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 6 absolute maximum ratings table 4 lists the absolute maximum ratings for the z86l825/826/827 microcontrol- lers. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this rati ng is a stress rating only. functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rat- ing conditions for an extended period may affect device reliability. 17 p21 input/output p20-27 are bit configurable as input or output. 18 p22 input/output p20-27 are bit configurable as input or output. 19 p23 input/output p20-27 are bit configurable as input or output. 20 p24 input/output p20-27 are bit configurable as input or output. table 4. absolute maximum ratings symbol description min max units v max supply voltage (*) ?0.3 +7.0 v t stg storage temperature ?65 +150 c t a oper. ambient temperature ? c notes: * voltage on all pins with respect to gnd ? see ?ordering information? on page 68. table 3. 20-pin dip, soic, and ss op pin identification (continued) 20-pin dip/soic/ssop standard mode direction description
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 7 standard test conditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to gnd. positive current flows into the referenced pin (figure 4). figure 4. test load diagram capacitance table 5 lists the capacitance for the z86l825/826/827 microcontrollers. . table 5. capacitance parameter max input capacitance 12 pf output capacitance 12 pf i/o capacitance 12 pf note: t a = 25c, v cc = gnd = 0v, f = 1.0 mhz, unmeasured pins returned to gnd. from output under test i
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 8 dc characteristics table 6 lists the direct current (dc) characteristics. table 6. dc characteristics t a = 0 c to +70 c symbol parameter v cc min max units conditions notes max input voltage 2.0 v 7 v i in <250 a 3.6 v 7 v i in <250 a v ch clock input high voltage 2.0 v 0.8 v cc v cc + 0.3 v driven by external clock generator 3.6 v 0.8 v cc v cc + 0.3 v driven by external clock generator v cl clock input low voltage 2.0 v v ss ?0.3 0.2 v cc v driven by external clock generator 3.6 v v ss ?0.3 0.2 v cc v driven by external clock generator v ih input high voltage 2.0 v 0.7 v cc v cc + 0.3 v 3.6 v 0.7 v cc v cc + 0.3 v v il input low voltage 2.0 v v ss ?0.3 0.2 v cc v 3.6 v v ss ?0.3 0.2 v cc v v oh1 output high voltage 2.0 v v cc ?0.4 v i oh = ?0.5 ma 3.6 v v cc ?0.4 v i oh = ?0.5 ma v oh2 output high voltage (p00, p01,p36) 2.0 v v cc ?0.8 v i oh = ?7 ma 3.6 v v cc ?0.8 v i oh = ?7 ma v ol1 output low voltage 2.0 v 0.4 v i ol = 1.0 ma 3.6 v 0.4 v i ol = 4.0 ma v ol2* output low voltage 2.0 v 0.8 v i ol = 5.0 ma 3.6 v 0.8 v i ol = 7.0 ma v ol2 output low voltage (p00, p01, p36) 2.0 v 0.8 v i ol = 10 ma 1 3.6 v 0.8 v i ol = 10 ma v offset comparator input offset voltage 2.0 v 25 mv 3.6 v 25 mv i il input leakage 2.0 v ?1 1 av in = 0 v , v cc 3.6 v ?1 1 av in = 0 v , v cc i ol output leakage 2.0 v ?1 1 av in = 0 v , v cc 3.6 v ?1 1 av in = 0 v , v cc
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 9 i cc supply current 2.0 v 10 ma @ 8.0 mhz 2, 3 3.6 v 15 ma @ 8.0 mhz 2, 3 2.0 v 250 a @ 32 khz 2, 3, 8 3.6 v 850 a @ 32 khz 2, 3, 8 i cc1 standby current (halt mode) 2.0 v 3 ma v in = o v , v cc @ 8.0 mhz 2, 3 3.6 v 5 ma same as above 2, 3 2.0 v 2 ma clock divide-by-16 @ 8.0 mhz 2, 3 3.6 v 4 ma same as above 2, 3 i cc2 standby current (stop mode) 2.0 v 8 av in = 0 v , v cc wdt is not running 4, 6, 9 3.6 v 10 a same as above 4, 6, 9 2.0 v 500 av in = 0 v , v cc wdt is running 4, 6, 9 3.6 v 800 a same as above 4, 6, 9 i lv standby current (low voltage) 2.0 v 15 a vcc < v bo 3.6 v 20 a same as above t por power-on reset 2.0 v 12 75 ms 3.6 v 5 20 ms v bo v cc low voltage protection 2.20 v 8 mhz max ext. clk freq. 5 notes: 1. all outputs excluding p00, p01, and p36 2. all outputs unloaded, inputs at rail. 3. cl1 = cl2 = 100 pf 4. same as note [4] except inputs at v cc . 5. the v bo increases as the temperature decreases. 6. oscillator stopped 7. oscillator stops when v cc falls below v lv limit 8. 32 khz clock driver input 9. wdt, comparators, low voltage detection, and adc (if applicable) are disabled. the ic might draw more current if any of the above peripherals is enabled. table 6. dc characteristics (continued) t a = 0 c to +70 c symbol parameter v cc min max units conditions notes
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 10 ac characteristics this section discusses the alternating curre nt (ac) characteristics. the timing dia- gram is shown in figure 5 and described in table 7. figure 5. timing diagram clock t in irq n clock setup stop mode recovery source 2 2 3 3 1 7 7 4 5 6 9 8 11 10
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 11 table 7. ac characteristics t a = 0c to +70c 8.0 mhz stop-mode recovery (d1, d0) number symbol parameter v cc min max units notes 1 tpc input clock period 2.0 v 121 dc ns 1 3.6 v 121 dc ns 1 2 trc,tfc clock input rise and fall times 2.0 v 25 ns 1 3.6 v 25 ns 1 3 twc input clock width 2.0 v 37 ns 1 3.6 v 37 ns 1 4 twtinl timer input low width 2.0 v 100 ns 1 3.6 v 70 ns 1 5 twtinh timer input high width 2.0 v 3tpc 1 5.5 v 3tpc 1 6 tptin timer input period 2.0 v 8tpc 1 3.6 v 8tpc 1 7 trtin,tftin timer input rise and fall times 2.0 v 100 ns 1 3.6 v 100 ns 1 8a twil interrupt request low time 2.0 v 100 ns 1, 2 3.6 v 70 ns 1, 2 8b twil interrupt request low time 2.0 v 5tpc 1 3.6 v 5tpc 1 9 twih interrupt request input high time 2.0 v 5tpc 1, 2 3.6 v 5tpc 1, 2 10 twsm stop-mode recovery width spec 2.0 v 12 ns 3.6 v 12 ns 2.0 v 5 tpc ns 3.6 v 5 tpc ns 11 tost oscillator start-up time 2.0 v 5tpc 4 3.6 v 5tpc 4
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 12 12 twdt watch-dog timer delay time 2.0 v 20 ms 5 0, 0 3.6 v 7.5 ms 5 2.0 v 20 ms 5 0, 1 3.6 v 7.5 ms 5 2.0 v 40 ms 5 1, 0 3.6 v 15 ms 5 (60 ms) 2.0 v 160 ms 5 1, 1 3.6 v 60 ms 5 notes: 1. timing reference uses 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0. 2. interrupt request through port 3 (p33?p31). 3. n/a 4. smr ? d5 = 0. 5. for internal rc oscillator. table 7. ac characteristics (continued) t a = 0c to +70c 8.0 mhz stop-mode recovery (d1, d0) number symbol parameter v cc min max units notes
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 13 pin functions xtal1 crystal 1 (time-based input) this pin connects a parallel-resonant crysta l, ceramic resonator, lc, or rc net- work or an external single-phase clock to the on-chip oscillator input. xtal2 crystal 2 (time-based output) this pin connects a parallel-resonant crys tal, ceramic resonant, lc, or rc net- work to the on-chip oscillator output. port 0 (p00,01,07) port 0 is a 3-bit, bidirectional, cmos-compatible port. these three i/o lines are configured under software control as a nibble i/o port. the output drivers are push-pull or open drain controlled by bit d2 in the pcon register. if one or both nibbles are required for i/o operation, they must be configured by writing to the port 0 mode register. after a hardware reset, port 0 is configured as an input port. a mask option is available to program 0.4 v dd cmos trip inputs on p00?p01. this allows direct interface to mouse/trackball ir sensors. port 0 has a 200 50%k ? s pull-up transistor built in. see figure 6. internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode. note:
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 14 figure 6. port 0 configuration p00, p01 (i/o) z86l82x mcu open-drain i/o v cc v cc 200 kohms pad out in in 0.4 v dd trip point buffer *mask selectable p07 (i/o)
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 15 port 2 (p27?p20) port 2 is an 8-bit, bidirectional, cmos-c ompatible i/o port. these eight i/o lines can be independently configured under softwa re control as inputs or outputs. port 2 is always available for i/o operation. a mask option is available to connect eight 200 k ? (50%) pull-up transistors on this port. bits programmed as outputs are globally programmed as either push-pull or open-drain. the por resets with the eight bits of port 2 configured as inputs. port 2 also has an 8-bit input or and an and gate that can be used to wake up the part. p20 can be programmed to ac cess the edge-detection circuitry in demodulation mode. see figure 7. figure 7. port 2 configuration port 2 i/o z86l82x mcu open-drain i/o mask option v cc 200 kohms pad out in
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 16 port 3 (p36?p31) port 3 (see figure 8) is a 5-bit, cmos-compatible port consisting of three fixed inputs (p33?p31) and two fixed outputs (p36 and p34). port 3 can be configured under software control for interrupt and output from the counter/timers. p31, p32, and p33 are standard cmos inputs; p34 and p36 are push-pull outputs. figure 8. port 3 configuration one on-board comparator processes analog signals on p32 with reference to the voltage on p33. the analog function is enabled by programming the port 3 mode register (bit 1). p31 and p32 are pr ogrammable as rising, falling, or both port 3 (i/o) z86l82x mcu r247 = p3m p31 p32 p33 p34 p36 + ? + ? 1 = analog 0 = digital p31 (an1) comp1 dig. an. pref d1 p32 (an2) comp1 p33 (ref2) from stop mode recovery source of smr irq2, p31 data latch irq0, p32 data latch irq1, p33 data latch
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 17 edge-triggered interrupts (irq register bits 6 and 7). p33 is the comparator refer- ence voltage input. access to the counter/timer edge-detection circuit is through p31 or p20 (see ?ctr1 register? on page 38). other edge-detect and irq modes are described in table 8. port 3 also provides output for the counter/timers and the and/or logic. control is performed by programming bits d5?d4 of ctr1 and bit 0 of ctr0. comparator inputs in analog mode, p32 and p33 have a comparator front end. the comparator refer- ence is supplied to p33. in this mode, the p33 internal data latch and its corre- sponding irq1 are diverted to the smr sources (excluding p31, p32, and p33) as indicated in figure 8. in digital mode, p 33 is used as d3 of the port 3 input reg- ister, which then generates irq1. comparators are powered down by entering stop mode. for p31?p33 to be used in a stop-mode recovery source, these inputs must be placed into digital mode. table 8. pin assignments pin i/o c/t comp. int. p31 in in an1 irq2 p32 in an2 irq0 p33 in rf2 irq1 p34 out t8 ao1 p36 out t8/16 p20 i/o in note:
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 18 figure 9. port 3 counter/timer output configuration + ? v dd pad p34 mux pcon, d0 v dd pad p36 mux out 36 t8/16_out ctr1, d0 mux p34 data t8_out p31 pref 1 comp 1 ctr0, d0
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 19 functional description the z86l82x incorporates special functi ons to enhance the z8's functionality in consumer and battery-operated applications. program memory the z86l82x family addresses 4/8/16 kb of internal program memory. the first 12 bytes are reserved for interrupt vectors. these locations contain the five 16-bit vectors that correspond to the five available interrupts. ram the z86l82x device has 237 bytes of ram that make up the register file. figure 10. program memory map (32k rom) expanded register file the register file has been expanded to al low for additional system control regis- ters and for mapping of additional peripher al devices into the register address area. the z8 register address space r0 through r15 has been implemented as location of first byte of instruction executed after reset 16383 12 11 10 9 8 7 6 5 4 3 2 1 0 not accessible on-chip rom reset start address irq5 irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 interrupt vector (lower byte) interrupt vector (upper byte)
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 20 16 banks of 16 registers per bank. these r egister groups are known as the erf (expanded register file). bits 7?4 of register rp select the working register group. bits 3?0 of register rp select the expanded register file bank. an expanded register bank is also referred to as an expanded register group (see figure 11). the upper nibble of the register pointer (figure 12 on page 22) selects which working register group of 16 bytes in the register file, out of the possible 256, is accessed. the lower nibble selects the expanded register file bank and, in the case of the z86l82x family, banks 0, f, and d are implemented. a 0h in the lower nibble allows the normal register file (bank 0) to be addressed, but any other value from 1h to fh exchanges the lower 16 registers to an expanded register bank. for example, for the z86l82x (see figure 11): r253 rp = 00h r0 = port 0 r1 = port 1 r2 = port 2 r3 = port 3 but if: r253 rp = 0dh r0 = ctrl0 r1 = ctrl1 r2 = ctrl2 r3 = reserved the counter/timers are mapped into erf group d. access is easily performed using the following: ld rp, #0dh ; select erf d for access to bank d ; (working register group 0) ld r0,#xx ; load ctrl0 ld 1, #xx ; load ctrl1 ld r1, 2 ; ctrl2 ctrl1 ld rp, #0dh ; select erf d for access to bank d ; (working register group 0) ld rp, #7dh ; select expanded register bank d ; working register group 7 of bank 0 ; for access. ld 71h, 2 ; ctrl2 register 71h ld r1, 2 ; ctrl2 register 71h note:
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 21 figure 11. expanded register file architecture uuuuuuuu register pointer 76543210 reset condition 76543210 register** expanded reg. bank (d) register** reset condition reset condition expanded reg. bank (f) register** working register group pointer z8 register file (bank 0)** expanded register bank group pointer reserved reserved expanded reg. group (0) register** reset condition u = unknown * not reset with a stop-mode recovery ** all addresses are in hexadecimal ? not reset with a stop-mode recovery, except bit 0. ff f0 7f 0f 00 * * * * ff fe fd fc fb fa f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 (f) 0f (f) 0e (f) 0d (f) 0c (f) 0b (f) 0a (f) 09 (f) 08 (f) 07 (f) 06 (f) 05 (f) 04 (f) 03 (f) 02 (f) 01 (f) 00 (d) 0c (d) 0b (d) 0a (d) 09 (d) 08 (d) 07 (d) 06 (d) 05 (d) 04 (d) 03 (d) 02 (d) 01 (d) 00 lvd hi8 lo8 hi16 lo16 tc16h tc16l tc8h tc8l reserved ctr2 ctr1 ctr0 u u u u u u u u u 0 0 0 u u u u u u u u u u 0 0 u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u 0 u 0 wdtmr reserved smr2 reserved smr reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved pcon u u 0 u u 0 0 u u u 1 u 0 0 0 u 0 0 0 u 0 0 0 u 0 0 0 u 0 0 0 u spl sph rp flags imr irq ipr p01m p3m p2m reserved reserved reserved reserved reserved reserved u u 0 u 0 0 u 0 0 1 u u u u 0 0 u u 0 u 0 0 u 1 0 1 u u u u 0 u u u 0 u 0 0 u 0 0 1 u u u u 0 u u u 0 u 0 0 u 0 0 1 u u u u 0 0 u u 0 u 0 0 u 1 0 1 u u u u 0 0 u u 0 u 0 0 u 1 0 1 u u u u 0 0 u u 0 u 0 0 u 0 0 1 u u u u 0 0 u u 0 u 0 0 u 1 0 1 u u u u 0 0 ? * * (0) 03 (0) 02 (0) 00 p3 p2 p0 0 u 0 u 0 u 0 u u u u u u u u u
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 22 figure 12. register pointer register expanded register file control registers (0d) figure 13, figure 14, and figure 15 show t he expanded register file control regis- ters (0d). figure 13. tc8 control register?(0d) oh: read/write except where noted r253 rp d7 d6 d5 d4 d3 d2 d1 d0 expanded register file pointer working register pointer default setting after reset = 0000 0000 d7 d6 d5 d4 d3 d2 d1 d0 0 = p34 as port output * * default setting after reset 1 = timer8 output 0 = disable t8 time-out interrupt 1 = enable t8 time-out interrupt 0 = disable t8 data capture interrupt 1 = enable t8 data capture interrupt 0 = disable t8 data capture interrupt 00 = sclk on t8 01 = sclk/2 on t8 10 = sclk/4 on t8 11 = sclk/8 on t8 r = 0 t8 disabled * r = 1 t8 counter time-out occurred w = 0 no effect w = 1 reset flag to 0 1 = single pass 0 = modulo-n r = 0 t8 disabled * r = 1 t8 enabled w = 0 stop t8 w = 1 enable t8 ctr1 (0d) 0h
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 23 figure 14. t8 and t16 common control functions?(0d) 1h: read/write d7 d6 d5 d4 d3 d2 d1 d0 transmit mode r/w 0 t16_out is 0 initially r/w 1 t16_out is 1 initially demodulation mode r 0 = no falling edge detection r 1 = falling edge detection w 0 = no effect w 1 = reset flag to 0 transmit mode r/w 0 = t8_out is 0 initially r/w 1 = t8_out is 1 initially demodulation mode r 0 = no rising edge detection r 1 = rising edge detection w 0 = no effect w 1 = reset flag to 0 transmit mode 0 0 = normal operation 0 1 = ping-pong mode 1 0 t16_out = 0 1 1 t16_out = 1 demodulation mode 0 0 = no filter 0 1 = 4 sclk cycle filter 1 0 = 8 sclk cycle filter 1 1 = reserved transmit mode/t8/t16 logic 0 0 = and 0 1 = or 1 0 = nor 1 1 = nand demodulation mode 0 0 = falling edge detection 0 1 = rising edge detection 1 0 = both edge detection 1 1 = reserved transmit mode 0 = p36 as port out put * 1 = p36 as t8/t16_out demodulation mode 0 = p31 as demodulator input 1 = p20 as demodulator input transmit/demodulation modes 0 = transmit mode * 1 = demodulation mode * default setting after reset ctr1 (0d) 1h note: care must be taken in differentiating note: changing from one mode to transmit mode from demodulation mode. depending on which of these two modes is operating, the ctr1 bit has different functions. another cannot be done without disabling the counter/timers.
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 24 figure 15. t16 control register?(0d) 2h: read/write except where noted d7 d6 d5 d4 d3 d2 d1 d0 0 = p35 is port output * * default setting after reset 1 = p35 is timer16 output 0 = disable t16 time-out interrupt 1 = enable t16 time-out interrupt 1 = enable t16 data capture interrupt 0 = disable t16 data capture interrupt 00 = sclk on t16 01 = sclk/2 on t16 10 = sclk/4 on t16 11 = sclk/8 on t16 r = 0 no t16 time-out r = 1 t16 time-out occurs w = 0 no effect w = 1 reset flag to 0 r = 0 t16 disabled * r = 1 t16 enabled w = 0 stop t16 w = 1 enable t16 ctr2 (0d) 02h transmit mode 0 = modulo-n for t16 1 = single pass for t16 demodulator mode 0 = t16 recognizes edge 1 = t16 does not recognize edge
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 25 expanded register file control registers (0f) figure 16 through figure 29 show the expanded register file control registers (0f). figure 16. stop-mode recovery register?(0f) 0bh: d6?d0 = write only, d7 = read only d7 d6 d5 d4 d3 d2 d1 d0 sclk/tclk divide-by-16 0 = off ** reserved (must be 0) stop-mode recovery source smr (0f) 0b 1 = on 000 = por only * 001 = reserved 010 = p31 011 = p32 100 = p33 101 = p27 110 = p2 nor 0?3 111 = p2 nor 0?7 stop delay 0 = off 1 = on* stop recovery level *** 0 = low * 1 = high stop flag 0 = por * 1 = stop recovery ** * default setting after reset ** default setting after reset and stop-mode recovery *** at the xor gate input
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 26 figure 17. stop-mode recovery register 2?(0f) 0dh: d2?d4, d6 write only figure 18. watch-dog timer register?(0f) 0fh: write only d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) stop-mode recovery source smr2 (0f) dh 000 = por only * 001 = nand p20, p21, p22, p23 010 = nand p20, p21, p22, p23, p24, p25, p26, p27 011 = nor p31, p32, p33 100 = nand p31, p32, p33 101 = nor p31, p32, p33, p00, p07 110 = nand p31, p32, p33, p00, p07 111 = nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level ** 0 = low * 1 = high * default setting after reset ** at the xor gate input reserved (must be 0) reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 wdt tap int rc osc * default setting after reset 00 = 7.5 ms min 01* = 7.5 ms min 10 = 15 ms min 11 = 60 ms min wdt during halt 0 = off 1 = on* wdt during stop 0 = off 1 = on* reserved (must be 0) wdtmr (0f) 0f
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 27 figure 19. port configuration register (pcon)?(0f) 0h: write only figure 20. port 2 mode register?f6h: write only figure 21. port 3 mode register?f7h: write only d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) reserved (must be 1) port 0 0 = open-drain 1 = push-pull* reserved (must be 1) *default setting after reset pcon (fh) 00h d7 d6 d5 d4 d3 d2 d1 d0 r246 p2m p27?p20 i/o definition 0 = defines bit as output 1 = defines bit as input * *default setting after reset d7 d6 d5 d4 d3 d2 d1 d0 r247 p3m 0 = port 2 open-drain * 1 = port 2 push-pull *default setting after reset 0 = p31, p32 digital mode 1 = p31, p32 analog mode reserved (must be 0)
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 28 r248 p01m figure 22. port 0 and 1 mode register (f8h: write only) d7 d6 d5 d4 d3 d2 d1 d0 p00?p03 mode 0: output 1: input * reserved; must be 0 reserved; must be 1 reserved; must be 0 p07?p04 mode 0: output 1: input * reserved; must be 0 * default setting after reset
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 29 figure 23. interrupt priority register?f9h: write only figure 24. interrupt request register?fah: read/write d7 d6 d5 d4 d3 d2 d1 d0 r249 ipr interrupt group priority 000 = reserved reserved (must be 0) 001 = c>a>b 101 = a>b>c 011 = a>c>b 100 = b>c>a 101 = c>b>a 110 = b>a>c 111 = reserved irq1, irq, priority (group c) 0 = irq1>irq4 1 = irq4>irq1 irq0, irq2, priority (group b) 0 = irq2>irq0 1 = irq0>irq2 irq3, irq5, priority (group a) 0 = irq5>irq3 1 = irq3>irq5 d7 d6 d5 d4 d3 d2 d1 d0 r250 irq irq0 = p32 input irq1 = p23 input irq2 = p31 input irq3 = t16 irq4 = t8 inner edge p31 p32 = 00 p31 p32 = 01 p31 p32 = 10 p31 p32 = 11
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 30 figure 25. interrupt mask register?fbh: read/write figure 26. flag regist er?fch: read/write d7 d6 d5 d4 d3 d2 d1 d0 r251 imr 1 = enables irq5?irq0 (d0 = irq0) reserved (must be 0) 0 = master interrupt disable * 1 = master interrupt enable ** * default setting after reset ** only by using e1, d1 instruction. d1 is required before changing the imr register. d7 d6 d5 d4 d3 d2 d1 d0 r252 flags user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 31 figure 27. register pointer?fdh: read/write figure 28. stack pointer high?feh: read/write figure 29. stack pointer low?ffh: read/write register file the register file (bank 0) consists of four i/o port registers, 237 general-purpose registers, and 16 control and status registers (r0?r3, r4?r239, and r240?255, respectively), plus two expanded register s groups (banks d and f). instructions can access registers directly or indirectly through an 8-bit address field, thereby allowing a short, 4-bit register address to use the register pointer (figure 30). in the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. the regi ster pointer addresses the starting location of the active working register group. working register group e0?ef can only be accessed through working registers and indirect addressing modes. d7 d6 d5 d4 d3 d2 d1 d0 expanded register bank pointer working register pointer r253 rp default setting after reset = 0000 0000 d7 d6 d5 d4 d3 d2 d1 d0 general purpose register byte (sp15?sp8) r254 sph d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp7?sp0) r255 spl note:
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 32 figure 30. register pointer stack the z86l82x internal register file is used for the stack. an 8-bit stack pointer (r255) is used for the internal stack that resides in the general-purpose registers (r4?r239). sph is used as a general-purpose register only when using internal stacks. when sph is used as a general-purpose register and port 0 is in address mode, the contents of sph are loaded into port 0 whenever the internal stack is accessed. 7f 70 6f 60 5f 50 4f 40 3f 30 2f 20 1f 10 0f 00 00 r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 the upper nibble of the register file address provided by the register pointer specifies the active working-register group r253 specified working register group the lower nibble of the register file address provided by the instruction points to the specified register register group 1 register group 2 i/o ports r15 to r0 r15 to r4* r3 to r0* note:
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 33 counter/timer registers table 9 describes the expanded register group d. hi8(d)0bh this register (table 10) holds the captured data from the output of the 8-bit counter/timer0. this register is typically used to hold the number of counts when the input signal is 1. l08(d)0ah this register (table 11) holds the captured data from the output of the 8-bit counter/timer0. this register is typically used to hold the number of counts when the input signal is 0hi16(d)09h. table 9. expanded register group d (d)0ch lvd (d)0bh hi8 (d)0ah lo8 (d)09h hi16 (d)08h lo16 (d)07h tc16h (d)06h tc16l (d)05h tc8h (d)04h tc8l (d)03h reserved (d)02h ctr2 (d)01h ctr1 (d)00h ctr0 table 10. hi8(d)0bh field bit position description t8_capture_hi 76543210 r w captured data no effect
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 34 . hi16(d)09h this register (table 12) holds the captured data from the output of the 16-bit counter/timer16. this register holds the ms-byte of the data. l016(d)08h this register (table 13) holds the captured data from the output of the 16-bit counter/timer16. this register holds the ls-byte of the data. tc16h(d)07h table 14 describes the counter/timer2 ms-byte hold register. table 11. l08(d)0ah field bit position description t8_capture_l0 76543210 r w captured data no effect table 12. hi16(d)09h field bit position description t16_capture_hi 76543210 r w captured data no effect table 13. l016(d)08h field bit position description t16_capture_lo 76543210 r w captured data no effect table 14. tc16h(d)07h field bit position description t16_data_hi 76543210 r/w data
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 35 tc16l(d)06h table 15 describes the counter/timer2 ls-byte hold register. tc8h(d)05h table 16 describes the counter/timer8 high hold register. tc8l(d)04h table 17 describes the counter/timer8 low hold register. table 15. tc16l(d)06h field bit position description t16_data_lo 76543210 r/w data table 16. tc8h(d)05h field bit position description t8_level_hi 76543210 r/w data table 17. tc8l(d)04h field bit position description t8_level_lo 76543210 r/w data
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 36 ctr0 counter/timer8 control register table 18 describes the ctr0 (d)00 counter/timer8 control register. t8 enable this field enables t8 when set (written) to 1. single/modulo-n when set to 0 (modulo-n), the counter reloads the initial value when the terminal count is reached. when set to 1 (single pass), the counter stops when the terminal count is reached. time-out this bit is set when t8 times out (terminal count reached). to reset this bit, a 1 must be written to this location. table 18. ctr0 (d)00 counter/timer8 control register field bit position value description t8_enable 7------- r w 0* 1 0 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------- r/w 0 1 modulo-n single pass time_out --5------ r w 0 1 0 1 no counter time-out counter time-out occurred no effect reset flag to 0 t8 _clock ---43--- r/w 0 0 0 1 1 0 1 1 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0 1 disable data capture int. enable data capture int. counter_int_mask ------1- r/w 0 1 disable time-out int. enable time-out int. p34_out -------0 r/w 0* 1 p34 as port output t8 output on p34 note: * indicates the value upon power-on reset.
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 37 writing a 1 is the only way to reset the terminal count status condition. therefore, you must reset this bit before using/enabling the counter/timers. care must be taken when using the or or and commands to manipulate ctr0, bit 5 and ctr1, bits 0 and 1 (demodulation mode). these instructions use a read-modify-write sequence in which the current status from the ctr0 and ctr1 registers is ored or anded with the designated value and then written back into the registers. for example, when the status of bit 5 is 1, a timer reset condition occurs. t8 clock this bit defines the frequency of the input signal to t8. capture_int_mask set this bit to allow an interrupt when data is captured into either lo8 or hi8 upon a positive or negative edge detection in demodulation mode. counter_int_mask set this bit to allow an interrupt when t8 has a time-out. p34_out this bit defines whether p34 is used as a normal output pin or the t8 output. ctr1(d)01h this bit controls the functions in common with the t8 and t16. caution: note:
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 38 ctr1 register table 19 describes the contents of the ctr1 register. table 19. ctr1 register field bit position value description mode 7------- r/w 0* transmit mode demodulation mode p36_out/demodulator_input -6------ r/w 0* 1 0 1 transmit mode port output t8/t16 output demodulation mode p31 p20 t8/t16_logic/edge _detect --54---- r/w 00 01 10 11 00 01 10 11 transmit mode and or nor nand demodulation mode falling edge rising edge both edges reserved transmit_submode/glitch_filter ----32-- r/w 00 01 10 11 00 01 10 11 transmit mode normal operation ping-pong mode t16_out = 0 t16_out = 1 demodulation mode no filter 4 sclk cycle 8 sclk cycle 16 sclk cycle
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 39 mode if it is 0, the counter/timers are in t he transmit mode; otherwise, they are in the demodulation mode. p36_out/demodulator_input in transmit mode, this bit defines whether p36 is used as a normal output pin or the combined output of t8 and t16. in demodulation mode, this bit defines whether the input signal to the counter/tim- ers is from p20 or p31. t8/t16_logic/edge_detect in transmit mode, this field defines how the outputs of t8 and t16 are combined (and, or, nor, nand). in demodulation mode, this field defines which edge needs to be detected by the edge detector. initial_t8_ou t/rising_edge ------1- r/w r w 0 1 0 1 0 1 transmit mode t8_out is 0 initially t8_out is 1 initially demodulation mode no rising edge rising edge detected no effect reset flag to 0 initial_t16_ou t/falling_edge -------0 r/w r w 0 1 0 1 0 1 transmit mode t16_out is 0 initially t16_out is 1 initially demodulation mode no falling edge falling edge detected no effect reset flag to 0 note: *default upon power-on reset table 19. ctr1 register (continued) field bit position value description
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 40 transmit_submode/glitch_filter in transmit mode, this field defines whether t8 and t16 are in the ?ping-pong? mode or in independent normal operation mode. setting this field to ?normal operation mode? terminates the ?ping- pong mode? operation. when set to 10, t16 is immediately forced to a 0; a se tting of 11 will force t16 to output a 1. in demodulation mode, this field defines the wi dth of the glitch that needs to be fil- tered out. initial_t8_out/rising_edge in transmit mode, if it is 0, the output of t8 is set to 0 when it starts to count. if it is 1, the output of t8 is set to 1 when it starts to count. when the counter is not enabled and this bit is set to 1 or 0, t8_out is set to the opposite state of this bit. this measure ensures that when the clock is enabled, a transition occurs to the initial state set by ctr1, d1. in demodulation mode, this bit is set to 1 when a rising edge is detected in the input signal. in order to reset it, a 1 must be written to this location. initial_t16 out/falling_edge in transmit mode, if it is 0, the output of t16 is set to 0 when it starts to count. if it is 1, the output to t16 is set 1 when it starts to count. this bit is effective only in normal or ping-pong mode (ctr1, d3, d2). when the counter is not enabled and this bit is set, t16_out will be set to the opposite state of this bit. this ensures that when the clock is enabled, a transition occurs to the initial state set by ctr1, d0. in demodulation mode, this bit is set to 1 when a falling edge is detected in the input signal. in order to reset it, a 1 must be written to this location. modifying ctr1 (d1 or d0) while the counters are enabled causes unpredictable output from t8/16_out. note:
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 41 ctr2 counter/timer16 control register table 20 describes the contents of the ctr2 register. t16_enable this field enables t16 when set to 1. single/modulo-n in transmit mode, when this bit is set to 0, the counter reloads the initial value when terminal count is reached. when this bit is set to 1, the counter stops when the terminal count is reached. table 20. ctr2 (d)02h: counter/timer16 control register field bit position value description t16_enable 7------- r w 0* 1 0 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------ r/w 0 1 0 1 transmit mode modulo-n single pass demodulation mode t16 recognizes edge t16 does not recognize edge time_out --5----- r w 0 1 0 1 no counter time-out counter time-out occurred no effect reset flag to 0 t16 _clock ---43--- r/w 00 01 10 11 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0 1 disable data capture int. enable data capture int. counter_int_mask ------1- r/w 0 disable time-out int. enable time-out int. reserve must be 0 -------0 r/w 0* reserved must be 0 note: * indicates the value upon power-on reset.
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 42 in demodulation mode, when this bit is set to 0, t16 captures and reloads on detection of all the edges. when this bit is set to 1, t16 captures and detects on the first edge, but ignores the subsequent edges. for details, see ?t16 demodula- tion mode? on page 50. time_out this bit is set when t16 times out (terminal count reached). in order to reset this bit, a 1 must be written to this location. t16_clock this bit defines the frequency of the input signal to counter/timer16. capture_int_mask set this bit to allow an interrupt when data is captured into lo16 and hi16. counter_int_mask set this bit to allow an interrupt when t16 times out. p35_out this bit is reserved. this bit must be 0. counter/timer functional blocks the following are the counte r/timer functional blocks: ? input circuit ? eight-bit counter/timer circuits (page 43) ? sixteen-bit counter/timer circuits (page 49) ? output circuit (page 53) input circuit the edge detector monitors the input signal on p31 or p20. based on ctr1 d5? d4, a pulse is generated at the pos edge or neg edge line when an edge is detected. glitches in the input signal t hat have a width less than specified (ctr1 d3, d2) are filtered out (see figure 31).
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 43 figure 31. glitch filter circuitry eight-bit counter/timer circuits figure 32 shows the 8-bit counter/timer circuits. figure 32. 8-bit counter/timer circuits ctr1 d5, d4 p31 p20 mux ctr1 d6 glitch filter edge detector pos edge neg edge ctr1 d3, d2 z8 data bus pos edge neg edge ctr0 d4, d3 sclk z8 data bus clock select clock 8-bit counter t8 tc8h tc8l ctr0 d2 irq4 ctr0 d1 t8_out hi8 lo8
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 44 t8 transmit mode before t8 is enabled, the output of t8 depends on ctr1, d1. if it is 0, t8_out is 1. if it is 1, t8_out is 0. when t8 is enabled, the output t8_out switches to the initial value (ctr1 d1). if the initial value (ctr1 d1) is 0, tc8l is loaded; otherwise, tc8h is loaded into the counter (see figure 33). in single-p ass mode (ctr0 d6), t8 counts down to 0 and stops, t8_out toggles, and the time-out status bit (ctr0 d5) is set. a time-out interrupt can be generated if it is enabled (ctr0 d1). see figure 34. in modulo-n mode, upon reaching terminal count, t8_out is toggled, but no inter- rupt is generated. then t8 loads a new count (if the t8_out level now is 0), tc8l is loaded; if it is 1, tc8h is loaded. t8 counts down to 0, toggles t8_out, sets the time-out status bit (ctr0 d5) and generates an interrupt if enabled (ctr0 d1). one cycle is thus completed. t8 then loads from tc8h or tc8l according to the t8_out level, and repeats the cycle. see figure 35.
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 45 figure 33. transmit mode flowchart t8 (8-bit) transmit mode no t8_enable bit set ctr0, d7 yes reset t8_enable bit load tc8l reset t8_out load tc8h set t8_out enable t8 no t8_timeout yes single pass single pass? modulo-n t8_out value 1 0 load tc8h set t8_out enable t8 no t8_timeout yes set time-out status bit (ctr0, d5) and generate timeout_int if enabled set time-out status bit (ctr0, d5) and generate temeout_int if enabled ctr1, d1 value load tc8l reset t8_out
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 46 figure 34. t8_out in single-pass mode figure 35. t8_out in modulo-n mode you can modify the values in tc8h or tc8l at any time. the new values take effect when they are loaded. to ensure know n operation, do not write these regis- ters at the time the values are to be loaded into the counter/timer. an initial count of 1 is not allowed (a nonfunction occurs). an initial count of 0 causes tc8 to count from 0 to ffh to feh. ?h? is used for hexadecimal values. transition from 0 to ffh is not a time-out condition. do not use the same instructions for stopping the counter/ timers and setting the status bits. two successive commands are necessary. first, the counter/timers must be stopped, and second, the status bits must be reset. these commands are required because it takes one counter/timer clock interval for the initiated event to actually occur. t8 demodulation mode you need to program tc8l and tc8h to ffh. after t8 is enabled, when the first edge (rising, falling, or both, depending on ctr1 d5, d4) is detected, it starts to count down. when a subsequent edge (rising, falling, or both depending on ctr1 d5, d4) is detected during counting, the current value of t8 is one's comple- mented and put into one of the capture registers. if it is a positive edge, data is put tc8h counts counter enable command, t8_out switches to its initial value (ctr1 d1) t8_out toggles time-out interrupt t8_out tc8l tc8h time-out interrupt counter enable command, t8_out switches to its initial value (ctr1 d1) t8_out toggles tc8l tc8h tc8l time-out interrupt note: caution:
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 47 into lo8; if it is a negative edge, hi8. one of the edge-detect status bits (ctr1 d1, d0) is set, and an interrupt can be generated if enabled (ctr0 d2). mean- while, t8 is loaded with ffh and starts counting again. if t8 reaches 0, the time- out status bit (ctr0 d5) is set, an interrupt can be generated if enabled (ctr0 d1), and t8 continues counting from ffh (see figure 36 and figure 37). figure 36. demodulation mode count capture flowchart no yes pos neg t8 lo8 t8 hi8 ffh t8 what kind of edge edge present t8_enable (set by user) t8 (8-bit) count capture no yes
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 48 figure 37. demodulation mode flowchart t8 (8-bit) demodulation t8 enable ctr0, d7 no yes ffh tc8 first edge present no yes enable tc8 disable t8 t8_enable bit set edge present no ye s t8 time-out no yes set edge present status bit and trigger data capture int. if enabled continue counting set edge present status bit and trigger time out int. if enabled mode no yes
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 49 sixteen-bit counter/timer circuits figure 38 shows the 16-bit counter/timer circuits. figure 38. 16-bit counter/timer circuits t16 transmit mode in normal or ping-pong mode, the output of t16, when not enabled, is dependent on ctr1, d0. if the result is a 0, t16_out is a 1; if it is a 1, t16_out is 0. you can force the output of t16 to either a 0 or 1 whether it is enabled or not by pro- gramming ctr1 d3, d2 to a 10 or 11. when t16 is enabled, tc16h * 256 + tc16l is loaded, and t16_out is switched to its initial value (ctr1 d0). when t16 counts down to 0, t16_out is toggled (in normal or ping-pong mode), an interrupt is generated if enabled (ctr2 d1), and a status bit (ctr2 d5) is set. global interrupts override this function as described in ?interrupts? on page 53. if t16 is in single-pass mode, t16 is stopped at this point (see figure 39). if t16 is in modulo-n mode, t16 is loaded with tc16h * 256 + tc16l and the counting continues (see figure 40). z8 data bus pos edge neg edge ctr2 d4, d3 sclk z8 data bus clock select clock 16-bit counter tc16h tc16l ctr2 d2 irq3 ctr2 d1 t16_out hi16 lo16 t16 note:
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 50 figure 39. t16_out in single-pass mode figure 40. t16_out in modulo-n mode you can modify the values in tc16h and tc16l at any time. the new values take effect when they are loaded. to ensure known operation, do not load these regis- ters at the time the values are to be loaded into the counter/timer. an initial count of 1 is not allowed. an initial count of 0 causes t16 to count from 0 to ffffh to fffeh. transition from 0 to ffffh is not a time-out condition. t16 demodulation mode you need to program tc16l and tc16h to ffh. after t16 is enabled, when the first edge (rising, falling, or both, depending on ctr1 d5, d4) is detected, t16 captures hi16 and lo16, re loads, and begins counting. if d6 of ctr2 is 0 when a subsequent edge (rising, falling, or both, depending on ctr1 d5, d4) is detected during counting, the current count in t16 is one's complemented and put into hi16 and lo16. when data is captured, one of the edge-detect status bits (ctr1 d1, d0) is set and an interrupt is generated if enabled (ctr2 d2). t16 is loaded with ffffh and starts again. this t16 mode is generally used to meas ure space time, the length of time between bursts of carrier signal (marks). tc16h*256+tc16l counts counter enable command, t16_out switches to its initial value (ctr1 d0) t16_out toggles time-out interrupt t16_out tc16h*256+tcl16 counter enable command, t16_out switches to its initial value (ctr1 d0) t16_out toggles, time-out interrupt t16_out toggles, time-out interrupt tc16h*256+tcl16 tc16h*256+tcl16
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 51 if d6 of ctr2 is 1 t16 ignores the subsequent edges in th e input signal and continues counting down. a time-out of t8 causes t16 to capture its current value and generate an interrupt if enabled (ctr2, d2). in this case, t16 does not reload and continues counting. if the d6 bit of ctr2 is toggled (by writing a 0 and then a 1 to it), t16 captures and reloads on the next e dge (rising, falling, or both, depending on ctr1 d5, d4) but continue to ignore subsequent edges. this t16 mode is generally used to measure mark times, the length of an active carrier signal bursts. when t16 reaches 0, it continues counti ng from ffffh. meanwhile, a status bit (ctr2 d5) is set, and an interrupt time-out can be generated if enabled (ctr2 d1). ping-pong mode this operation mode (see figur e 41) is only valid in transmit mode. t8 and t16 must be programmed in single-pass mode (ctr0 d6, ctr2 d6), and ping-pong mode must be programmed in ctr1 d3, d2. you can begin the operation by enabling either t8 or t16 (ctr0 d7 or ct r2 d7). for example, if t8 is enabled, t8_out is set to this initial value (ctr1 d1). according to t8_out's level, tc8h or tc8l is loaded into t8. after the termi nal count is reached, t8 is disabled, and t16 is enabled. t16_out switches to its initial value (ctr1 d0), data from tc16h and tc16l is loaded, and t16 starts to count. after t16 reaches the termi- nal count, it stops, t8 is enabled again, and the whole cycle repeats. interrupts can be allowed when t8 or t16 reaches term inal control (ctr0 d1, ctr2 d1). to stop the ping-pong operation, write 00 to bits d3 and d2 of ctr1. enabling ping-pong operation while the counter/timers are running might cause intermittent counter/timer function. disable the counter/timers and then reset the status flags before instituting this operation. note:
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 52 figure 41. ping-pong mode starting ping-pong mode first, make sure both counter/timers are not running. then set t8 into single- pass mode (ctr0 d6), set t16 into si ngle-pass mode (ctr2 d6), and set the ping-pong mode (ctr1 d2, d3). these instructions do not have to be in any par- ticular order. finally, start ping-pong mode by enabling either t8 (ctr0 d7) or t16 (ctr2 d7). during ping-pong mode the enable bits of t8 and t16 (ctr0 d7, ctr2 d7) are set and cleared alter- nately by hardware. the time-out bits (ctr0 d5, ctr2 d5) are set every time the counter/timers reach the terminal count. enable tc8 time-out enable tc16 time-out ping-pong ctr1, d3, d2
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 53 output circuit figure 42 shows the output circuit. figure 42. output circuit interrupts the z86l82x features six different interrupts. the interrupts are maskable and prioritized, as shown in figure 43. the si x sources are divided as follows: three sources are claimed by port 3 lines p33? p31, two by the counter/timers, and one by lvd (see table 21). the interrupt ma sk register, globally or individually, enables or disables the six interrupt requests. mux mux mux and/or/nor/nand logic t8_out t16_out ctr1 d2 ctr1 d3 ctr1 d5, d4 ctr1 d6 p36 ctr0 d0 p36_internal p34 p34_internal
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 54 figure 43. interrupt block diagram table 21. interrupt types, sources, and vectors name source vector location comments irq0 p32 0,1 external (p32), rising falling edge triggered irq1 p33 2,3 external (p33), falling edge triggered irq2 p31, t in 4,5 external (p31), risin g falling edge triggered irq3 t16 6,7 internal irq4 t8 8,9 internal p31 p32 p33 irq register d6, d7 interrupt edge select timer timer low voltage irq2 imr global interrupt enable interrupt request vector select 16 8 detection 5 irq0 irq1 irq3 irq4 irq5 ipr priority logic irq
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 55 when more than one interrupt is pending, priorities are resolved by a programma- ble priority encoder controlled by the interrupt priority register. an interrupt machine cycle is activated when an interrupt request is granted. as a result, all subsequent interrupt are disabled, and the program counter and status flags are saved. the cycle then branches to the program memory vector location reserved for that interrupt. all z86l82x interrupts are vectored through locations in the pro- gram memory. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. to accommo- date polled interrupt systems, interrupt inputs are masked, and the interrupt request register is polled to determine which of the interrupt requests require ser- vice. an interrupt resulting from an1 is mapped into irq2, and an interrupt from an2 is mapped into irq0. interrupts irq2 and irq0 can be rising, falling, or both edge triggered, and are programmable by the user. the software can poll to identify the state of the pin. programming bits for the interrupt edge select are located in the irq register (r250), bits d7 and d6. the configuration is indicated in table 22. clock the z86l82x on-chip oscillator has a hi gh-gain, parallel-resonant amplifier for connection to a crystal, lc, ceramic reso nator, or any suitable external clock source (xtal1 = input, xtal2 = output). the crystal must be at cut, 1 mhz to 8 mhz maximum, with a series resistance (rs) less than or equal to 100 ohms. the z86l82x on-chip oscillator can be driven with a low-cost rc network or other suit- able external clock source. table 22. irq register irq interrupt edge d7 d6 irq2(p31) irq0 (p32) 00 f f 01 f r 10 r f 11r/fr/f notes: f = falling edge r = rising edge in stop mode, the comparators are turned off.
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 56 for 32-khz crystal operation, an external feedback resistor (rf) and a serial resis- tor (rd) are required. see figure 44. figure 44. oscillator configuration the crystal needs to be connected across xtal1 and xtal2 using the recom- mended capacitors (capacitance greater than or equal to 22 pf) from each pin to ground. the rc oscillator configuration is an external resistor connected from xtal1 to xtal2, with a frequency-setting capacitor from xtal1 to ground (see figure 44). power-on reset (por) a timer circuit clocked by a dedicated on-board rc oscillator is used for the power-on reset (por) timer func tion. the por time allows v cc and the oscilla- tor circuit to stabilize before instruction execution begins. the por timer circuit is a one-shot timer triggered by one of three conditions: ? power fail to power ok status including waking up from v bo standby ? stop-mode recovery (if d5 of smr = 1) ? wdt time-out c1 c2 xtal1 xtal2 l r rf rd c1 c1 c1 c2 c2 xtal1 xtal2 xtal1 xtal2 xtal1 xtal2 xtal1 xtal2 ceramic resonator or crystal c1, c2 = 47pf typ* f = 8 mhz lc c1, c2 = 22 pf l = 130 h* f = 3 mhz* rc @ 3v vcc (typ) c1 = 33 pf* r = 1k* 32 khz xtal c1 = 20 pf, c = 33 pf rd = 56?470k rf = 10m external clock
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 57 the por time is a nominal 5 ms. bit 5 of the stop-mode register determines whether the por timer is bypassed after stop-mode recovery (typical for external clock, rc, and lc oscillators). halt halt turns off the internal cpu clock, but not the xtal oscillation. the counter/ timers and external interrupts irq0, irq1, irq2, irq3, and irq4 remain active. the devices are recovered by interrupts, either externally or internally generated. an interrupt request must be executed (enabled) to exit halt mode. after the interrupt service routine, the program continues from the instruction after the halt. stop this instruction turns off the internal cl ock and external crystal oscillation and reduces the standby current to 10 a or less. stop mode is terminated only by a reset (such as wdt time-out), por, smr, or external reset. this termination causes the processor to restart the application program at address 000ch. to enter stop (or halt) mode, you need to first flush the instruction pipeline to avoid suspending execution in mid-instructio n. to execute this action, you must execute a nop (op code = ffh) immediately before the appropriate sleep instruc- tion. for example: ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 58 port configuration register (pcon) the pcon register configures the comparator output on port 3. it is located in the expanded register 2 at bank f, location 00, as shown in figure 45. figure 45. port configuration register (pcon)?write only port 0 output mode (d2) bit 2 controls the output mode of port 0. a 1 in this location set the output to push- pull, and a 0 sets the output to open-drain. stop-mode recovery register (smr) this register selects the clock divide value and determines the mode of stop- mode recovery (figure 46). all bits are write only except bit 7, which is read only. bit 7 is a flag bit that is hardware set on the condition of stop recovery and reset by a power-on cycle. bit 6 controls whether a low level or a high level at the xor- gate input is required from the recovery source. bit 5 controls the reset delay after recovery. bits d2, d3, and d4, or the smr register, specify the source of the stop- mode recovery signal. bit d0 determines if sclk/tclk (shown in figure 47) are divided by 16 or not. the smr is located in bank f of the expanded register group at address 0bh. d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) reserved (must be 1) port 0 0 = open-drain 1 = push-pull* reserved (must be 1) *default setting after reset pcon (fh) 00h
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 59 figure 46. stop-mode recovery register figure 47. sclk circuit d7 d6 d5 d4 d3 d2 d1 d0 sclk/tclk divide-by-16 0 = off 1 = on reserved (must be 0) stop-mode recovery source 000 = por only * 001 = reserved 010 = p31 011 = p32 100 = p33 101 = p27 110 = p2 nor 0?3 111 = p2 nor 0?7 stop delay 0 = off 1 = on * stop recovery level *** 0 = low * 1 = high stop delay 0 = por * 1 = stop recovery ** * default setting after reset ** default setting after reset and stop-mode recovery *** at the xor gate input smr (0f) 0b osc divide by 2 divide by 16 sclk tclk smr, d0
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 60 sclk/tclk divide-by-16 select (d0) d0 of the smr controls a divide-by-16 prescaler of sclk/tclk. the purpose of this control is to selectively reduce dev ice power consumption during normal pro- cessor execution (sclk control) and/or halt mode (where tclk sources inter- rupt logic). after stop-mode recovery, this bit is set to a 0. stop-mode recovery source (d2, d3, and d4) these three bits of the smr specify the wake-up source of the stop recovery (figure 48 and table 23 on page 62).
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 61 figure 48. stop-mode recovery source smr d4 d3 d2 v cc p31 p32 p33 to irq1 s3 s4 p27 p20 p23 p20 p27 smr d6 00 0 smr d4 d3 d2 10 0 smr d4 d3 d2 11 1 smr d4 d3 d2 10 1 smr d4 d3 d2 01 1 smr d4 d3 d2 00 1 smr d4 d3 d2 11 0 smr d4 d3 d2 10 0 smr d4 d3 d2 01 0 smr d4 d3 d2 00 0 smr d4 d3 d2 11 1 smr d4 d3 d2 10 1 smr d4 d3 d2 01 1 smr d4 d3 d2 00 1 smr d4 d3 d2 11 0 s1 s2 smr2 d6 p20 p23 p20 p27 p31 p32 p33 p31 p32 p33 p31 p32 p33 p00 p07 p31 p32 p33 p20 p21 p22 p31 p32 p33 p00 p07 v cc to reset and wdt circuitry (active low)
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 62 any port 2 bit defined as an output drives the corresponding input to the default state to allow the remaining inputs to control the and/or function. refer to ?stop-mode recovery register 2 (smr2)? on page 63 for other recover sources. stop-mode recovery delay select (d5) this bit, if low, disables the 5-ms reset delay after stop-mode recovery. the default configuration of this bit is one. if the ?fast? wake up is selected, the stop- mode recovery source must be kept active for at least 5tpc. stop-mode recovery edge select (d6) a 1 in this bit position indicates that a high level on any one of the recovery sources wakes the z86l82x from stop mode. a 0 indicates low level recovery. the default is 0 on por. cold or warm start (d7) this bit is read only. it is set to 1 when the device is recovered from stop mode. the bit is set to 0 when the device is reset other than stop-mode recovery. table 23. stop-mode recovery source smr:432 operation d4 d3 d2 description of action 0 0 0 por and/or external reset recovery 0 0 1 reserved 0 1 0 p31 transition 0 1 1 p32 transition 1 0 0 p33 transition 1 0 1 p27 transition 1 1 0 logical nor of p20 through p23 1 1 1 logical nor of p20 through p27 note:
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 63 stop-mode recovery register 2 (smr2) this register determines the mode of stop-mode recovery for smr2 (see figure 49). figure 49. stop-mode recovery register 2?(0f) dh:d2?d4, d6 write only if smr2 is used in conjunction with smr, either of the specified events causes a stop-mode recovery. port pins configured as outputs are ignored as a smr or smr2 recovery source. for example, if the nand or p23?p20 is selected as the recovery source and p20 is configured as an output, the remaining smr pins (p23?p21) form the nand equation. table 24 describes the contents of the stop-mode recovery register 2. d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) reserved (must be 0) stop-mode recovery source 000 = por only * 001 = nand p20, p21, p22, p23 010 = nand p20, p21, p22, p33, p24, p25, p26, p27 011 = nor p31, p32, p33 100 = nand p31, p32, p33, p00, p07 101 = nor p31, p32, p33, p00, p07 110 = nand p31, p32, p33, p00, p07 111 = nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level ** 0 = low * 1 = high * default setting after reset ** at the xor gate input reserved (must be 0) smr2 (0f) dh note:
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 64 watch-dog timer mode register (wdtmr) the wdt is a retriggerable, one-shot timer that resets the z8 if it reaches its ter- minal count. the wdt must initially be enabled by executing the wdt instruction and refreshed on subsequent executions of the wdt instruction. the wdt circuit is driven by an on-board rc oscillator or external oscillator from the xtal1 pin. the wdt instruction affects the zero (z), sign (s), and overflow (v) flags. the por clock source is selected with bit 4 of the wdt register. bits 0 and 1 con- trol a tap circuit that determines the mi nimum time-out period. bit 2 determines whether the wdt is active during halt, and bit 3 determines wdt activity during stop. bits 5 through 7 are reserved (figure 50). this register is accessible only during the first 60 processor cycles (122 xtal clocks) from the execution of the first instruction after power-on-reset, watch-dog reset, or a stop-mode recov- ery (figure 50). after this point, the register cannot be modified by any means, intentional or otherwise. the wdtmr cannot be read and is located in bank f of the expanded register group at address location 0fh. the wdtmr is organized as shown in figure 50. table 24. smr2(f)0dh: stop-mode recovery register 2 field bit position value description reserved 7------- 0 reserved (must be 0) recovery level -6------ w0* 1 low high reserved --5----- 0 reserved (must be 0) source ---432-- w 000* 001 010 011 100 101 110 111 a. por only b. nand of p23?p20 c. nand or p27?p20 d. nor of p33?p31 e. nand of p33?p31 f. nor of p33?p31, p00, p07 g. nand of p33?p31, p00, p07 h. nand of p33?p31, p22?p20 reserved ------10 00 reserved (must be 0) notes: *indicates the value upon power-on reset port pins configured as outputs are ignored as a smr recovery source.
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 65 figure 50. watch-dog timer mode register?write only wdt time select (d0, d1) this bit selects the wdt time period. it is configured as indicated in table 25. wdtmr during halt (d2) this bit determines whether or not the wd t is active during halt mode. a 1 indi- cates active during halt. the default is 1. table 25. wdt time select d1 d0 time-out of internal rc osc 0 0 7.5 ms min 0 1 7.5 ms min 10 15 ms min 11 60 ms min notes: tpc = xtal clock cycle. the default on reset is 7.5 ms. d7 d6 d5 d4 d3 d2 d1 d0 wdt tap int rc osc * default setting after reset 00 = 7.5 ms min 01* = 7.5 ms min 10 = 15 ms min 11 = 60 ms min wdt during halt 0 = off 1 = on* wdt during stop 0 = off 1 = on* reserved (must be 0) wdtmr (0f) 0f
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 66 wdtmr during stop (d3) this bit determines whether or not the wd t is active during stop mode. since the xtal clock is stopped during stop mode, the on-board rc has to be selected as the clock source to the wdt/ por counter. a 1 indicates active during stop. the default is 1. clock source for wdt (d4) this bit determines which oscillator source is used to clock the internal por and wdt counter chain. if the bit is a 1, the in ternal rc oscillator is bypassed, and the por and wdt clock source is driven from the external pin, xtal1. the default configuration of this bit is 0, which selects the rc oscillator. see figure 51. figure 51. resets and wdt + ? 5 clock filter *clr2 clk 18 clock reset generator reset internal reset active high wdt tap select ck source select (wdtmr) xtal internal rd osc. m u x por 7.5 ms 15 ms 60 ms 7.5 ms clk *clr1 wdt/por counter chain v dd vbo/vlv 2v ref. wdt from stop mode recovery source 12 ns glitch filter stop delay select (smr) v cc low operating voltage det.
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 67 mask selectable options there are seven mask selectable options to choose from based on rom code requirements. these are listed in table 26. brown-out voltage/standby an on-chip voltage comparator checks that the v cc is at the required level for correct operation of the device. reset is globally driven when v cc falls below v bo . a further small drop in v cc causes the xtal1 and xtal2 circuitry to stop the crystal or resonator clock. typical low-vo ltage power consumpion in this low volt- age standby mode (i lv ) is about 20 a. if the v cc is allowed to stay above vram, the ram content is preserved. when the power level is returned to above v bo , the device performs a por and functions normally. table 26. mask selectable options rc/other rc/xtal 32 khz xtal on/off port 20?27 pull-ups on/off port 31?33 pull-ups on/off port 3 mouse mode 0.4 v dd trip on/off
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 68 ordering information figure 52 shows the 20-pin soic package diagram. figure 53 on page 69 shows the 20-pin dip package diagram. figur e 54 on page 70 shows the 20-pin ssop package diagram. figure 52. 20-pin soic package diagram
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 69 figure 53. 20-pin dip package diagram
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 70 figure 54. 20-pin ssop package diagram z86l825/826/827 for fast results, contact your local zilog sales office for assistance in ordering the part desired. ordering code rom size package temperature z86l825pz008sc 4k pdip 0 c to +70 c z86l826pz008sc 8k pdip 0 c to +70 c Z86L827PZ008SC 16k pdip 0 c to +70 c z86l825sz008sc 4k soic 0 c to +70 c z86l826sz008sc 8k soic 0 c to +70 c z86l827sz008sc 16k soic 0 c to +70 c z86l825hz008sc 4k ssop 0 c to +70 c z86l826hz008sc 8k ssop 0 c to +70 c z86l827hz008sc 16k ssop 0 c to +70 c
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 71 codes figure 55 shows an example of what the ordering codes represent. figure 55. ordering codes example package p = plastic dip s = soic (small outline integrated circuit) h = ssop (shrink small outline package) temperature s = 0 c to +70 c speed 8 = 8.0 mhz environmental c = plastic standard precharacterization product the product represented by this document is newly introduced and zilog has not completed the full characterization of the product. the document states what zilog knows about this product at this time, but additional features or nonconfor- mance with some aspects of the document may be found, either by zilog or its customers in the course of further application and characterization work. in addi- tion, zilog cautions that delivery may be uncertain at times, due to startup yield issues. example: z 86l825 s z 008 s c is a z86l825, soic, 8 mhz, 0 c to 70 c, plastic standard flow environmental flow temperature speed reserved package product number zilog prefix
z86l825/826/827 20-pin low-voltage ir microcontrollers ps008808-1203 p r e l i m i n a r y 72 customer feedback form z86l825/826/827 20-pin low- voltage ir microcontrollers if you experience any problems while operating this product, or if you note any inaccura- cies while reading this product specification, please copy and complete this form, then mail or fax it to zilog (see return information , below). we also welcome your sugges- tions! customer information product information return information zilog system test/customer support 532 race street san jose, ca 95126-3432 fax: (408) 558-8300 web address: www.zilog.com problem description or suggestion provide a complete description of the problem or your suggestion. if you are reporting a specific problem, include all steps leading up to the occurrence of the problem. attach additional pages as necessary. _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ name country company phone address fax city/state/zip email serial # or board fab #/rev # software version document number host computer description/type

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